The present invention relates generally to the field of integrated circuit design, and more specifically to identifying delayed equivalences within an integrated circuit.
An integrated circuit can be designed to include a plurality of latches. Often, these circuits are designed using a single latch model for all of the latches in a circuit. Using a single latch model can simplify the design constraints on the integrated circuit. However, in other cases, particularly when there is little logic between two pipeline stages, different latch models may be used to meet certain needs of the circuit. For example, latch models that consume less power can be implemented selectively to minimize the power consumption of the entire circuit. In some cases, different latch models may be clock gated differently.